1. Field of the Invention
The present invention relates to an oscillation stop detection circuit to be used for an electronic device including a built-in oscillation circuit, for detecting a state in which the oscillation circuit stops oscillating.
2. Description of the Related Art
Some electronic devices including a built-in oscillation circuit are provided with an oscillation stop detection circuit for determining whether the oscillation circuit is normally oscillating. When the oscillation stops, the oscillation circuit is restarted or a system is reset immediately.
FIG. 4 illustrates a circuit diagram of a related-art oscillation stop detection circuit. The related-art oscillation stop detection circuit includes inverters 10, 11, and 12, an NMOS transistor 20, a PMOS transistor 30, a capacitor 40, a positive power supply terminal 1, an input terminal 3, a constant voltage terminal 4, and an output terminal 7. An output of the inverter 10 is represented by a node B, and an input of the inverter 12 is represented by a node C.
FIG. 5 is a timing chart illustrating an operation of the related-art oscillation stop detection circuit. An oscillation signal IN is input to the input terminal 3, and a signal in anti-phase with the oscillation signal IN is output to the node B via the inverter 10. When the oscillation signal IN is Low, the node B becomes High to turn on the NMOS transistor 20, thereby charging the capacitor 40 to set the node C to Low. A constant voltage Vref is input to the constant voltage terminal 4. When the oscillation signal IN is High, the node B becomes Low to turn off the NMOS transistor 20, thereby discharging the capacitor 40 to increase the voltage at the node C. When the oscillation signal IN has the amplitudes of High and Low, the node C repeatedly charges and discharges the capacitor 40 to output a signal of High as a signal STOPX to the output terminal 7 via the inverter 12. When the oscillation signal IN stops oscillating and becomes a signal of Low, the voltage at the node C continues to increase. When the voltage at the node C exceeds an inversion level of the inverter 12, the output of the inverter 12 is inverted so that a signal of Low is output from the output terminal 7. In this manner, it can be detected that the oscillation signal IN has stopped oscillating (see, for example, Japanese Patent Application Laid-open No. 2005-252873).
In the related-art oscillation stop detection circuit, however, in the case where a signal obtained by frequency-dividing an original oscillation of the oscillation circuit by a frequency divider circuit or the like is input to the input terminal 3, there is a problem in that the stop of oscillation cannot be detected because it cannot be known whether the signal of the input terminal 3 stops at High or Low when the original oscillation of the oscillation circuit stops. Further, it is difficult to accurately measure an oscillation stop detection period that starts from the stop of the oscillation circuit and ends when a signal is output to the output terminal 7. In addition, there is another problem in that, when the input terminal 3 is Low, a current flows from the PMOS transistor 30 to the NMOS transistor 20 and an NMOS transistor of the inverter 11, resulting in large current consumption.